Learn RISC-V 64-bit (RV64) - Interactive Tutorial

What is RISC-V 64-bit (RV64)?

RISC-V is an open standard instruction set architecture (ISA) based on reduced instruction set computing (RISC) principles. RV64 is the 64-bit version, supporting 64-bit registers, addresses, and data types. It is widely used in modern processors for its simplicity, extensibility, and open ecosystem.

Base ISA: RV64I (Integer instructions, 64-bit)
Extensions: M (Multiply/Divide), A (Atomic), F/D (Floating Point), C (Compressed), and more
Registers: 32 integer (x0-x31), 32 floating-point (f0-f31)
Endianness: Little-endian by default

This tutorial covers the basics and lets you interactively explore and test your knowledge!

Instruction Formats

Type	Fields	Description
R-type	opcode, rd, funct3, rs1, rs2, funct7	Register-register operations
I-type	opcode, rd, funct3, rs1, imm[11:0]	Immediate, loads, jalr, system
S-type	opcode, imm[4:0], funct3, rs1, rs2, imm[11:5]	Stores
B-type	opcode, imm[11], imm[4:1], funct3, rs1, rs2, imm[10:5], imm[12]	Branches
U-type	opcode, rd, imm[31:12]	LUI, AUIPC
J-type	opcode, rd, imm[20\|10:1\|11\|19:12]	JAL

RV64I adds 64-bit operations and immediate fields are sign-extended to 64 bits where applicable.

Core Integer Instructions (RV64I)

Name	Format	Description
ADD, SUB	R	rd = rs1 + rs2 / rd = rs1 - rs2
SLL, SRL, SRA	R	Shift left/right logical/arithmetic
SLT, SLTU	R	Set if less than (signed/unsigned)
AND, OR, XOR	R	Bitwise logic
ADDI, SLLI, SRLI, SRAI	I	Immediate arithmetic/shift
SLTI, SLTIU	I	Set if less than immediate
ANDI, ORI, XORI	I	Immediate bitwise logic
LB/LH/LW/LWU/LD	I	Load byte/half/word/word unsigned/double
SB/SH/SW/SD	S	Store byte/half/word/double
BEQ/BNE/BLT/BGE/BLTU/BGEU	B	Conditional branches
LUI/AUIPC	U	Load upper immediate / Add upper immediate to PC
JAL/JALR	J/I	Jump and link / Jump and link register
ECALL/EBREAK	I	System call / Break
64-bit only: ADDIW, SLLIW, SRLIW, SRAIW	R/I	Word (32-bit) arithmetic/shift, sign-extended to 64 bits

Standard Extensions

RV64M (Multiply/Divide)

MUL, MULH, MULHSU, MULHU: 64-bit multiply variants
DIV, DIVU, REM, REMU: 64-bit divide/remainder
MULW, DIVW, DIVUW, REMW, REMUW: 32-bit word operations, sign-extended to 64 bits

RV64A (Atomic)

LR.D/SC.D: 64-bit load-reserved/store-conditional
AMOs: 64-bit atomic memory operations

RV64F/D (Floating Point)

FLD/FSD: 64-bit floating-point load/store
FMV.D.X, FMV.X.D: Move between int and double
All single-precision (F) and double-precision (D) arithmetic

RV64C (Compressed)

16-bit compressed forms for common 64-bit instructions

Register ABI (RV64)

Register	ABI Name	Description
x0	zero	Zero constant
x1	ra	Return address
x2	sp	Stack pointer
x3	gp	Global pointer
x4	tp	Thread pointer
x5-x7	t0-t2	Temporaries
x8	s0/fp	Saved/frame pointer
x9	s1	Saved register
x10-x11	a0-a1	Function args/return values
x12-x17	a2-a7	Function args
x18-x27	s2-s11	Saved registers
x28-x31	t3-t6	Temporaries

Floating Point Registers

f0-7: ft0-7 (temporaries)
f8-9: fs0-1 (saved)
f10-11: fa0-1 (args/return)
f12-17: fa2-7 (args)
f18-27: fs2-11 (saved)
f28-31: ft8-11 (temporaries)